1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices having a plurality of banks.
2. Description of the Background Art
Conventionally there exist semiconductor memory devices having a plurality of banks. In such semiconductor memory devices, each bank includes a plurality of memory cells arranged in rows and columns, and a plurality of words lines corresponding to a plurality of rows and a plurality of bit lines corresponding to a plurality of columns. The banks can be activated and inactivated (or precharged) substantially independent of each other.
In such a semiconductor memory device, initially at a selected bank the data on a bit line pair connected to a selected word line is differentially amplified by a sense amplifier. Then, when a write/read instruction is received, a designated bit line pair and a data input/output line pair are electrically connected together. Thus data is written to a selected memory cell or data is read from a selected memory cell.
A data input/output line pair and a bit line pair are not allowed to be electrically connected together until a predetermined period of time elapses after a sense amplifier is activated.
This is because a period of time is required for the sense amplifier to sufficiently amplify a slight potential difference between the paired bit lines. Allowing a sense amplifier to amplify a potential difference between paired bit lines for longer periods of time ensures that the sense amplifier more reliably amplifies the potential difference between the paired bit lines.
On the other hand, according to a specification of the semiconductor device a read/write command can be input after a defined period tRCD elapses following the activation of a bank. As such, a bit line pair and a data input/output line pair must be allowed to be connected together if the defined period of time tRCD is satisfied.
As such, in a conventional semiconductor memory device a bit line pair and a data input/output line pair are connected together in response to a control signal (an interlock signal) output from a connection control circuit 900 shown in FIG. 10.
As shown in FIG. 10, connection control circuit 900 includes a delay stage 901 configured of inverters 902A, 902B, . . . and 902M, an inverter 903, and an NAND circuit 904. Inverters 902A, 902B, . . . and 902M are connected in series. Inverter 902A receives a sense amplifier activation signal .phi.N. Delay stage 901 delays sense amplifier activation signal .phi.N to output a signal .phi.X. NAND circuit 904 receives sense amplifier activation signal .phi.N and signal .phi.X. Inverter 903 inverts an output from NAND circuit 904 and outputs an interlock signal CE.
Sense amplifier activation signal .phi.N is provided to activate a sense amplifier. When a row select operation starts, a selected bank's sense amplifier activation signal .phi.N is driven high, which is received by a sense amplifier, which amplifies a potential difference between paired bit lines connected thereto.
As shown in FIG. 11, when sense amplifier activation signal .phi.N is driven high and a delay time (.DELTA.D) provided by delay stage 901 then elapses, interlock signal CE is driven high.
When interlock signal CE is driven high, a selected column (a bit line pair) and a data input/output line pair are electrically connectable together via a gate (not shown). As such, when a sense amplifier is activated and a predetermined period of time .DELTA.D then elapses a bit line pair and a data input/output line pair can be connected together.
However, if the conventional connection control circuit 900 is used interlock signal CE is activated at a timing determined depending on delay stage 901. As such, interlock signal CE would be activated at an offset timing depending on a condition of process, temperature or voltage. Thus it has been difficult to satisfy the defined period of time tRCD as well as ensure a sufficient margin.